A Layout-Aware Methodology for Path-Delay Fault Grading and Diagnosis | Consortium for Embedded Systems | SIU

Abstract: The deep-submicron effects are becoming more prominent with technology scaling and thereby, pose new challenges for effective grading and diagnosis of faults. Guaranteeing coverage for various abnormalities in an Integrated Circuit(IC) is a daunting task. Proposed here is a methodology to perform a layout-aware grading for Path Delay Faults (PDF) so as to characterize path criticalities based on each path’s sensitivity to a given set of parameters. Furthermore, to diagnose potential failures that can result due to variations in a parameter or a set of parameters.

Problem:
1. Implicit layout-aware grading of path-delay faults.
2. Characterizing path criticalities based on layout information.
3. Diagnosis of potential faults with respect to a target parameter.

Rationale / Approach:
1. With continued scaling of devices and interconnects the behavior of an Integrated Circuit (IC) has become more sensitive to manufacturing processes, environmental variations and other uncertainties.
2. Certain uncertainties such as power supply noise and crosstalk, which are pattern dependent, contribute to the worsening signal integrity issues in modern ICs.
3. The quality of a test set should be determined not only by the timing behavior of the paths detected by the test set but also the sensitivity of such paths to the variations in process and environmental parameters.
4. Failure analysis/Diagnosis should be able to leverage layout information in order to identify potential defects.
5. We propose to determine the quality of a given test set in identifying the defects arising from process and environmental variations.
6. Additionally, we propose to build an infrastructure that can perform effective diagnosis using information from the layout.

Novelty:
1. Non enumerative grading for PDFs and implicitly annotating paths with layout information.
2. Metrics to determine test set quality using layout information.
3. Effective failure analysis using layout information.

Potential Member Company Benefits:
1. A layout-aware path grading tool to estimate the quality of a given test set.
2. A new layout-aware metric for calculating test set quality.
3. A tool for effective failure analysis by leveraging layout information.

Deliverables for the proposed year:
1. Software tool to perform layout-aware path grading and thereby, estimate test set quality.
2. Software tool to aid failure analysis using layout information.