Adaptive Compressive Sensing Techniques for Low Power Sensors

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PIs: Haibo Wang, Spyros Tragoudas
Type: Continuing
Proposed Budget: $50,000
Phone: (618) 453-1522, (618) 453-7645
Email: haibo@engr.siu.edu, spyros@engr.siu.edu

Abstract: The objective of this project is to investigate novel adaptive approaches to more effectively apply compressive sensing (CS) techniques in low-power sensor systems. Recently, CS emerged as an attractive technique in low-power sensor development, because of its capability to allow sensor signals to be sampled at rates lowers than Nyquist rate. In CS method, the number of sampled compressive signals is selected according to the sparseness of the sensor signals. Currently, the majority of CS circuits use fixed sampling rates during the entire sensing operations. To further reduce the power consumption of sensors using compressive sensing, we have been investigating the potentials of adaptively adjusting the sampling rates used in compressive sensing methods at system level. As a natural extension to the current effort, the proposed research is to investigate circuit techniques to execute adaptive CS. Particularly, we will investigate the use of low-power analog wavelet transformation circuit to detect when sampling rate can be changed in adaptive CS.

Problem: For a compressible sensor signal X (containing N sampled data points), which has K significant terms projected into domain . The required size (M) of the sampled compressive sensor output (Y) is ( log ) N M K K   . Currently, most CS circuits are designed with fixed M values. However, if signal sparsity changes during sensor expected life cycle, this may result in different K values and hence it is desirable to use different M values. For CS circuits designed for fixed M values, such variations potentially degrade sensor performance in terms of either accuracy or power efficiency

Rationale / Approach: We have been investigating the sparsity variations for signals collected by biomedical sensors. Our study indicates that signal sparsity varies over the time and at different operating conditions. We are also working on estimating the potential power saving if the sampling rate used in compressive sensors can be adaptively adjusted according to signal sparsity variations, which also indicates that adaptive CS is an attractive technique for further reducing power consumption of sensor nodes. An import question that needs to be answered in the implementation of adaptive CS is how to detect the
signal sparsity changes and subsequently adjust the sampling rate. To tackle this question, the proposed research investigates the use of low-power analog wavelet transformation circuit to detect when sampling rate can be changed in adaptive CS. We will first develop a low-power analog wavelet transformation circuit using a 0.13m CMOS technology. Circuit simulation will be performed with ECG and EEG signals as inputs. Through extensive circuit simulations, we aim to establish the relations between the analog WT circuit output and the sparsity of the signals. With the established relations, we will further investigate the effectiveness of using the analog WT circuit to determining the sampling rates in adaptive CS.

Novelty: Compressive sensing is a relatively new approach to reduce the power consumption of certain type sensors. The proposed work helps make compressive sensing more power efficiency, hence advances the state of the art of compressive sensing.

Potential Member Company Benefits: The developed techniques have the potentials to help member companies further reduce the power consumptions of certain sensor devices in productions or used in their research and development (R&D) projects.

Deliverables for the proposed year:
1. Design of the analog wavelet transformation circuit
2. Investigation results on the effectiveness of using analog wavelet transformation circuit to determine the sampling rates in adaptive compressive sensing

Milestones for the proposed year:
1. Quarter 1 (08/13-10/13): Finalize the structure and complete the key optimization issues for the circuit to be designed Quarter 2 (11/13-01/14): Complete the circuit design
2. Quarter 3 (02/13-04/13): Establish the relation between circuit output and signal sparsity via extensive simulations
3. Quarter 4 (05/13-07/14): Investigate the effectiveness of the proposed approach