Exploiting 3D IC Platform to Realize Low Power and High Performance Image/Video Processing | Consortium for Embedded Systems | SIU

Abstract: Enabled by the emerging three-dimensional (3D) integration technologies, 3D stacked IC has a great potential of extending the Moore’s low into nanoscale era and realizing next-generation embedded computing systems [1]. Since the 3D IC memory family became standard in 2013 [2] and logic-in-memory products will be available in market in 2015 [3-5], it is increasingly feasible and very attractive to design full embedded computing systems in 3D IC platform. With the great features of 3D IC platform, it is potential to design and realize advanced embedded computing (such as image processing) within the constraints and requirements of power, performance, latency and footprint.

In the proposed research, the motivation is to fully explore 3D IC hardware platform and to achieve low-power, high-quality, and energy-efficient image/video processing. We focus on architecture & algorithm level innovation, as well as system implementation of advanced image processing in 3D IC logic-in-memory platform. The outcomes of this research include: (1) new image processing architecture & algorithm, (2) entire system implementation and design evaluation.

Problem: Low-power, high-performance, and low-latency are expected in next-generation embedded computing systems, such as image processing. Existing SoC hardware approaches are difficult to meet all the end-user requirements, such as multi-channel I/O, low-latency, large image sizes, high frame rates, small system footprint, and low power consumption. The emerging 3D stacked logic-in-memory hardware is an attractive and increasingly feasible option of embedded computation platform, which enables high memory density (X6), large energy savings (X5), high memory bandwidth (4TB/s), and small system footprint (X8). With these great features of 3D stacked IC, it is potential to design and realize advanced embedded computing (such as image processing) within the constraints and requirements of power, performance, latency and footprint.

Since the state-of-art of 3D stacked logic-in-memory IC has been presented recently in industry, the proposed research aims to explore architecture and algorithm level innovation of image processing in the 3D stacked logic-in-memory platform. We will explore and develop new data storage and management algorithms for motion estimation, which is a critical block in next-generation high efficiency video coding (HEVC). Through a case study, we plan to demonstrate how 3D IC logic-in-memory platform benefits embedded computing and enables low-power, low latency and high performance image/video processing tasks.

Rationale / Approach: To address these challenges of image/video processing, our approach is to co-optimize the algorithm, architecture and hardware. We will revise the image/video processing algorithms to match the underlying 3D memory-in-logic hardware platform and adapt the necessary modeling and design framework.

Novelty: 3D IC hardware platform is a new emerging approach to reduce the power consumption of SoC embedded systems. The proposed work helps explore architecture & algorithm-level design techniques, hence advances the state of the art of next-generation of low-power, high-performance and energy-efficient image/video processing.

Potential Member Company Benefits: The proposed project will be a preliminary study and example of shifting current SoC embedded computation systems into future 3D IC hardware platform. The proposed project will result in significant reduction of hardware cost and improvement of energy efficiency in image/video processing systems. The proposed design techniques are also applicable to other computation and memory-hungry applications in 3D IC platform.

Deliverables for the proposed year: 1. Design of new image processing architecture and algorithm
2. Entire system implementation and design evaluation.

Milestones for the proposed year: Q1: Exploration of existing research in the area of 3D IC memory-in-logic platform, Q2: Select a set of image/video processing algorithms, Q3: Implement and optimize image processing algorithms on 3D IC memory-in-logic platform, Q4: entire system implementation and evaluation.