Debugging Errors in Failed Functional Test Sequences
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PIs: Spyros Tragoudas, Themistoklis Haniotakis
Type: New
Budget: $50,000
Phone: (618) 453-7027
Email: spyros@engr.siu.edu, haniotak@engr.siu.edu
Abstract: Proposed is a formulation for quick diagnosis of the sources of failure in a failing system level test when functional input sequences are applied. The formulation tries to determine the possible combinations of multiple defects in the device that justify the observed output error sequence. These failures may correspond to one of the following: defects that escaped structural tests, defects in the untested parts of the circuit that lack scan coverage (shadow logic around SRAM), functional defects that are triggered only when particular sequence of input is applied.
Problem: 1. Identify the set of all possible input test sequences for a given output functional sequence using implicit function based methods
2. Defect isolation in integrated circuits by performing error analysis on a given set of input and output functional test sequences at the RTL abstraction of integrated circuits
Rationale / Approach: 1. Traditional ATPG methods fail to detect many potential defects in the increasingly complex modern integrated circuits
2. The process of debugging defects emanating during system level tests involves intensive manual labor and time. This makes it challenging to achieve the ever shrinking time-to-market.
3. Scalability issues diagnosis at the gate level are alleviated by approaching the problem at a higher level of abstraction like the Register Transfer (RT) level.
4. The approach works by modeling error combinations at the outputs of the hierarchical RT level modules and propagating the errors to justify the observed erroneous output.
Novelty: 1. Use of implicit function based methods in identifying the set of all possible input test sequences corresponding to a given output sequence
2. Isolation of defects independent of fault model
3. Quick defect isolation due to reduced complexity at the RT level abstraction of the circuit
Potential Member Company Benefits: 1. Effective techniques to avoid the painstaking manual debug of system level test failures
2. Quick defect isolation and diagnostic test generation
Deliverables for the proposed year:
1. Software tool to implicitly identify input test sequences using function based methods
2. Software tool to perform defect isolation and diagnostic test generation at the RT level