Ground Work for Embedding a Field Oriented Motor Controller into a Single System on a Chip | Consortium for Embedded Systems | SIU

Abstract: This project will develop a high performance SoC FPGA with embedded microprocessor and logic to implement a field oriented control (FOC) motor drive. The SoC includes a multi core micro-processor and an FPGA. The FPGA will incorporate the low level computationally intensive parts of the controller; the micro-processor will integrate the high level control functions and the supervisory functions. The proposed work will develop a suitable implementation of the FOC into the FPGA. The main problems addressed by this work include achieving high control band-width and closed-loop accuracy under the limited resources of the FPGA. The results of this investigation can be later extended to build and test a complete prototype system.

Problem: Motor drives often require fast-acting control loops in order to achieve fast, accurate and stable response. Particularly for FOC the computation requirements can be intense. Therefore, conventional implementations based on digital processors or micro-controllers may not always provide the control bandwidth necessary for the application. On the other hand, SoC FPGA systems with embedded processing offer the capability for fast computation and increased data acquisition rates. The project will investigate the design of a FOC loop into a SoC which combines a micro-processor and an FPGA.

Rationale / Approach: The work performed by the project will provide results that can be used for building a complete motor control system. The proposed work will develop a suitable mathematical model for design a stable FOC loop with the desired response characteristics. Subsequently, the designed loop will be transferred onto the FPGA. The FPGA configuration will include a set of registers allocated for values such as gains, controller parameters and controller set points that will be furnished by the supervisory micro-processor, which is part of the SoC. In order to obtain the optimum outcome, studies will conducted to investigate the trade-off between the bit size of the number representation in the FPGA versus available resources inside the FPGA and versus the resulting control bandwidth reduction, noise sensitivity and parameter error sensitivity.

Novelty: The novelty of the proposed project lies in the development of design methods for an FPGA-based FOC and in the combination of digital microcontroller and logic within an FPGA which is expected to provide improved flexibility for motor controller design.

Potential Member Company Benefits: The project will lay the groundwork for a subsequent development and testing of a complete motor drive controller including high-level functions. The project benefits electronics, heavy machinery, aerospace and other industries.

Deliverables for the proposed year: The following are the project deliverables:
(a) Integration of the RDC into the FPGA;(b) An FPGA-based FOC algorithm.