Spyros Tragoudas

Main Content

Spyros Tragoudas

Director, SIU Site
Principal Investigator, SIU
Phone: (618) 453-7027
Email: spyros@engr.siu.edu

Dr. Tragoudas’ current research interests are in VLSI Design Automation, Verification and Validation of Embedded Systems, Emerging Technologies, Hardware Security.

 


I:  EDUCATION

  • 1986 Diploma (5 years), Computer Engineering and Informatics Department, University of Patras, Patras, Greece.
  • 1988 M.S., Erik Jonsson School of Engineering and Computer Science, Computer Science Program, The University of Texas at Dallas, Richardson, TX 75083-0688.
  • 1991 Ph.D., Erik Johnson School of Engineering and Computer Science, Computer Science Program, The University of Texas at Dallas, Richardson, TX 75083-0688.

II:  EMPLOYMENT RECORD

  • 07/01/01 to date  Professor, Electrical and Computer Engineering Department, Southern Illinois University, Carbondale, IL 62901.
  • 03/01/09 to date  Director, National Science Foundation (NSF) Industry/University Cooperative Research Center (I/UCRC) for Embedded Systems, SIUC-site.
  • 07/16/99 - 06/30/01 Associate Professor (tenured), Electrical and Computer Engineering Department, Southern Illinois University, Carbondale, IL 62901.
  • 08/16/98-07/15/99 Associate Professor (tenured), Electrical and Computer Engineering Department, The University of Arizona, Tucson, AZ 85721.
  • 07/01/96-08/15/98 Associate Professor (tenured), Computer Science Department, Southern Illinois University, Carbondale, IL 62901.
  • 07/01/97-08/15/98 Graduate Program Director, Computer Science Department, Southern Illinois University, Carbondale, IL 62901.
  • 08/15/91-06/30/96 Assistant Professor, Computer Science Department, Southern Illinois University, Carbondale, IL 62901.
  • 01/03/87-08/14/91 Research/Teaching Assistant, Computer Science Program, School of Engineering and Computer Science, The University of Texas at Dallas, Richardson, TX 75083-0688.
  • 08/15/86-01/02/87 Systems Analyst, Computer Technology Institute, Patras, Greece.

III:  RESEARCH INTERESTS

  • Design and test automation for VLSI circuits and systems
  • Cyber-physical systems (embedded systems, computer/network security, sensor networks)

IV: PROFESSIONAL AFFILIATIONS

  • Senior member of the IEEE (member since 1987)
  • ACM (1987-1992)
  • ISCA (1991-1999, 2010 – to date)
  • HKN (since 2011)

V:  EDITORIAL SERVICE

  • IEEE Transactions on Computers (2007 to date)
  • VLSI Design (1997- 1999, 2007 to date)
  • Research Letters in Electronics (2008 to date)
  • Journal of Electrical and Computer Engineering (2010 to date)
  • Journal of Universal Computer Science (1995 to date)
  • ISRN Electronics ( 2011 to date)

VI:  LEADERSHIP POSITIONS HELD 
University centers
•    Director, NSF I/UCRC for embedded systems at SIUC (2009 – to date)
University constituencies and committees

  • Chair of the Graduate Council, SIUC (2007-2008)
  • Chair, Dean Selection Committee, College of Engineering, SIUC (2004-2005)
  • Chair, Outstanding Scholar Award Selection Committee, SIUC (2001-2002)

Professional conferences

  • General Chair, IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2010, October 6-8, 2010, Kyoto, Japan
  • Program Chair, IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2010, October 7-9, 2009, Chicago, IL

VII:  HONORS AND AWARDS
Scholar Awards

  • Excellence through Commitment: Outstanding Scholar Award for the College of Eng.,  SIUC (2004).
  • K.E. Tempelmeyer Outstanding Faculty Research Award, College of Engineering SIUC (2004).
  • Shaphiro Scholar, Dartmouth College, May 1993.

Best paper awards in peer-reviewed conference proceedings 

  • Color Counting Technique and Its Applications to Path Delay Fault Coverage (with J. Deodhar), Proc. IEEE International Symposium on Quality of Electronic Design (ISQED), pp. 378-383, San Jose CA, March 2001.
  • Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms (with D. Kagaris, and D. Karayiannis), Proc. of the 1997 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), pp. 366-371, Austin TX, October 1997.
  • A Class of Good Characteristic Polynomials for LFSR Test Pattern Generators (with D. Kagaris), Proc. of the 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD), Design and Test Track, Boston MA, October 1994.
  • Nomination: On-Chip Deterministic Counter-based TPG with Low Heat Dissipation (with X. Kavousianos, and D. Nikolos), 1999 Southwest Symposium on Mixed Signal Design.

 

VIII:  RESEARCH GRANTS RECEIVED
Federal & Industry Research Grants (excluding equipment)

  1. NSF I/UCRC for Embedded Systems at SIUC – Phase II (period 4/15/16-3/31/17): $265,000 ($40,000 from NSF IIP 1361847, and $225,000 at BP241169 from Intel, Ford Motor Company, United Technologies Aerospace Systems, Lemko.)
  2. Collaborative Research: Scalable and Power-Efficient Compressive Sensing CMOS Image Sensors and Reconstruction Circuits, $99,999 , National Science Foundation, IIP 1535658, PI: S. Tragoudas, co-PI: H. Wang, (co-PIs at ASU: S. Vrudhula and  J-S Seo - $100,000), 10/01/15 – 9/30/17.
  3. NSF I/UCRC for Embedded Systems at SIUC – Phase II (period 4/15/15-3/31/16): $215,000 ($40,000 from NSF IIP 1361847, and $175,000 at BP241169 from Intel, Ford Motor Company, United Technologies Aerospace Systems.)
  4. State Graph Traversal with Hamiltonian Paths, $39,853, Naval Surface Warfare Center Crane Division, CRNBAA14-001, (BP 225475), PI: S. Tragoudas, 8/16/14- 8/15/15.
  5. NSF I/UCRC for Embedded Systems at SIUC – Phase II (period 4/15/14-3/31/15): $231,000 ($40,000 from NSF IIP 1361847, $16,000 from NSF for REU IIP 1447290, and $175,000 at BP241169 from Intel, Ford Motor Company, United Technologies Aerospace Systems.)
  6. Collaborative Research: Testability and Timing Analysis in Nanoscale Designs in the presence of Process Variations, $100,000, National Science Foundation, IIP 1432026, PI: S. Tragoudas, co-PI: S. Th. Haniotakis, (co-PI at ASU: S. Vrudhula - $100,000), 9/15/14 - 9/15/16.
  7.  Low Power Built-In Self-Testing circuits toward Prognostic Sensors, $50,000 (SIUC share $50,000), National Science Foundation, IIP 1331309, CORBI between the I/UCRC for Embedded Systems (SIUC) and the I/UCRC on Intelligent Maintenance Systems (U Cincinnati), PI: S. Tragoudas, co-PI: H. Wang, (co-PI at U. Cincinnati: J. Lee - $50,000), 8/1/2013-2/28/2015,
  8. NSF I/UCRC for Embedded Systems at SIUC (period 3/13-2/14): $315,000 ($50,000 from NSF IIP 0856039, $16,000 from NSF for REU IIP 1341839, and $249,000 at BP241169 from Intel, Rockwell Collins, United Technologies Aerospace Systems.)
  9. Collaborative Research: Synthesis and Design of Robust Threshold Logic Circuits, $200,000 (SIUC share $100,000), National Science Foundation (IIP-1230757), 8/1/2012 - 7/31/2014, PI: S. Tragoudas, co-PIs: S. Vrudhula (ASU) and H. Wang (SIUC).
  10. NSF I/UCRC on Embedded Systems at SIUC (period 3/11-2/12), $346,000, PI S. Tragoudas ($50,000 from NSF IIP 1230757, $16,000 from NSF IIP 1134925, and $280,000 at BP241169 from Intel, Rockwell Collins, Hamilton-Sundstrand, Caterpillar, General Dynamics, EMAC and Dickey-john).
  11. NSF  I/UCRC on Embedded Systems at SIUC (period 3/10-2/11), $287,000, PI S. Tragoudas  ($50,000 from NSF IIP 1230757, $8,000 from NSF CCF 1020333, and $229,500 at BP241169 from Intel, Wildlife Materials , Caterpillar, NAVSEA, EMAC, SAIC, and Dickey-john).
  12. NSF I/UCRC on Embedded Systems at SIUC (period 3/09-2/10), $170,000, PI S. Tragoudas ($50,000 from NSF IIP 1230757 and $120,000 at BP 241169 from Intel, Wildlife Materials and SAIC).
  13. Collaborative Research: Synthesis, Verification and Testing for Nano-CMOS and Beyond using Threshold Logic, $320,910 (SIUC share: $100,000), National Science Foundation (CCF-0702628), 9/1/2007 - 8/31/2011. PI: S. Vrudhula, PI at SIUC: S. Tragoudas, co-PI: H. Wang.
  14. Collaborative Research: Synthesis, Verification and Testing for Nano-CMOS and Beyond using Threshold Logic, $12,000, National Science Foundation (CCF-1020334), 5/28/10 - 8/31/11. PI: S. Tragoudas.
  15. Collaborative Research: Consortium for Embedded Systems at SIUC, planning grant, $10,000, National Science Foundation (IIP-0700757), 3/13/2007 - 1/31/2008. PI: S. Tragoudas.
  16. IED Location Estimation System, Science Applications International Corporation, $29,000, 2/09 – 12/09. PI: S. Tragoudas.
  17. Delay Fault Testing in Deep Submicron, $209,500, Qualcomm Incorporated, 5/16/05 - 5/15/10. PI: S. Tragoudas.
  18. Path Delay Fault Grading for Large Test Sequences, $10,000, Intel Corporation, 1/15/09-1/15/10. PI: S. Tragoudas.
  19. Path Delay Fault Grading for Large Test Sequences, $90,000, Intel Corporation, 6/16/05 - 6/15/08. PI: S. Tragoudas.
  20. Prototype to Estimate Location of an RF Source, $100,000, Naval Surface Warfare Center, CRANE, BAA N00164-05-R-0001, 10/1/2007 - 9/30/2008. PI: S. Tragoudas, co-PIs: W. Osborne and F. Harackiewicz.
  21. Early Clock Architectures for High Performance Busses, $35,000, Intel Corporation, 5/15/07-5/15/10. PI: S. Tragoudas.
  22. Effect Cause Diagnosis for Path Delay Faults, $5,272, Intel Corporation, 6/1/07- 8/15/07. PI: S. Tragoudas
  23. Path Delay Fault Grading for Large Test Sequences, $20,000, Intel Corporation, 6/15/04 - 6/14/2005. PI:  S. Tragoudas, co-PI: Th. Haniotakis.
  24. Testing for Delay Faults for Digital ICs, $10,000, Intel Corporation, 01/01/04- 12/31/04. PI: S. Tragoudas, co-PI: Th. Haniotakis.
  25. Built-In Self-Test Mechanisms and Embedded Cores, $255,829, National Science Foundation, Design Automation Program (CCR-9815229, re-named as CCR-0096119), 8/16/98-6/31/02. PI: S. Tragoudas, co-PI: D. Kagaris
  26. REU: Built-In Self-Test Mechanisms and Embedded Cores, $25,000, National Science Foundation (REU supplement to CCR-0096119), Design Automation Program. PI: S. Tragoudas, co-PI: D. Kagaris, Jan. 2000 –Sept. 2000.
  27. REU: Built-In Self-Test Mechanisms and Embedded Cores, $10,000, National Science Foundation, (REU supplement to CCR-9815229), Design Automation Program, 7/00-7/01. PI: S. Tragoudas, co-PI: D. Kagaris.
  28. Incorporation of Datapath portions in the Controller during High-Level Synthesis, $44,228, View Logic Systems Incorporated, Fremont CA, July 1997. PI: S. Tragoudas.
  29. Built-In Test Pattern Generation Methods, $89,171, National Science Foundation, Design, Tools and Test Program (MIP-9409905), 7/94 -7/97. PI: S. Tragoudas.
  30. REU: Built-In Test Pattern Generation Methods, $10,000 National Science Foundation, (supplement to MIP 9409905) 7/95-7/96. PI: S. Tragoudas.
  31. LFSR based Test Pattern Generation, $12,000, Design Automation Conference Graduate Scholarship, June 1993. PI: S. Tragoudas.

Equipment grants & donations (Hardware & Software)

  • Tesla C2705 P1030-AA02 GF110 Geberic 6 GB GPUs, Nvidia Corporation, (valued by Nvidia at $1,389), 2/8/12. PI: S. Tragoudas
  • Synopsys Electronic Design Automation Software, Synopsys Inc.,  (valued at $64,214,500 by Synopsys), 1/15/09, PI: S.Tragoudas.
  • 2 PCs from Intel for research on funded project “Early Clock Architectures for High Performance Busses” (valued $5,000 by Intel), 7/07, PI: S. Tragoudas.
  • Synopsys Electronic Design Automation Software, Synopsys Inc., (value adjusted to $37,778,400 by the SIUC Foundation), 2/13/07, PI: S.Tragoudas.
  • HP 83000 F330t IC tester, (valued at $360,000), Qualcomm Incorporated, 5/05, PI: S. Tragoudas.
  • Vertex Xilinx FPGA Boards and Software, (valued at $244,295 by Xilinx), Xilinx Corporation, Grant number XUP-18677), 7/02, co-PIs: S. Tragoudas and H. Wang (Research projects: Detecting Path Delay Faults on RAM-based FPGAs by S. Tragoudas,  and  Mixed-Signal Field Programmable Devices  by H. Wang).
  • SunBlade 1000: Equipment Grant, $20,102, National Science Foundation, Dec. 2001, PI: S. Tragoudas
  • Sun Blade 1000: Equipment matching grant to NSF, $10,051, Sun Microsystems, Dec. 2001, PI: S. Tragoudas
  • Synopsys Design Tool Package, Synopsys Inc., (valued by Synopsys at $14,800,000, adjusted by the Dean of CoE to a $ 2,000,000 grant), Jan. 2000, PI: S. Tragoudas.

Internal (SIUC) funding

  • Matching funds for the NSF I/UCRC for Embedded Systems , $21,000 ($7,000 annually), office eof the VCR, SIUC. PI: S. Tragoudas
  • Path Delay Fault Grading for Large Test Sequences, $20,000, Matching Grant by the MTC at SIUC, 6/16/04 - 6/15/05. PI:S. Tragoudas, co-PI: Th. Haniotakis.
  • LFSR based Test Pattern Generation for Random Logic, $16,078, ORDA (currently ASPA)  at SIUC, 7/94-7/95. PI: S. Tragoudas, co-PI: D. Kagaris.

 

IX:  PEER REVIEWED PUBLICATIONS 
Recent Peer-Reviewed Journal Articles

  1. A. M. Somashekhar and S. Tragoudas, Diagnosis of Performance Limiting Segments in Integrated Circuits using Path Delay Measurements, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), accepted for publication.
  2. A. M. Somashekhar, S. Tragoudas, R. Jaybharathi, and S. Gangadhar, Non-enumerative Generation of Path Delay Distributions and its Applocation to Critical Path Selection, ACM Transactions on Design Automation of Electronic Systems, accepted for publication.
  3. A. K. Palaniswamy, S. Tragoudas, and Th. Haniotakis, ATPG for Delay Defects in Current Mode Threshold Logic Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), accepted for publication.
  4. S. Mohanty and S. Tragoudas, Scalable Off - Line Searches in DNA sequences, ACM Journal on Emerging Technologies in Computing (JETC), pp. 18:1 – 18:25, vol. 11, issue 2, November 2014.
  5. J. Lenox and S. Tragoudas, Adapting an Implicit Path Delay Grading Method for Parallel Architectures, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1965 - 1976, vol. 33, no. 12, December 2014.
  6. K. Karmakar and S. Tragoudas, Error Correction Encoding for Tightly coupled On-Chip Buses, IEEE Transactions on VLSI Systems (TVLSI), pp. 2571-2584, vol. 22, no. 12, December 2014.
  7. A.K. Palaniswamy  and S.Tragoudas,  Improved threshold logic synthesis using implicant-implicit algorithms, ACM Journal on Emerging Technologies in Computing (JETC), pp. 21:1- 21:32, vol. 10, issue 3, April 2014.
  8. K. Karmakar and S. Tragoudas, On-Chip Codeword Generation to Cope with Crosstalk, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , vol. 33, no. 2, pp 237-250, Feb. 2014.
  9. L. Pierce and S. Tragoudas, Nanopipelined Threshold Network Synthesis, ACM Journal on Emerging Technologies in Computing (JETC), vol. 10, no. 2, pp. 17:1-17:17, February 2014.
  10. S. Gangadhar and S. Tragoudas, A Probabilistic Approach to Diagnose SETs in Sequential Circuits, Journal of Electronic Testing:  Theory and Applications (JETTA), vol. 29, pp. 317-330, March 2013.
  11. L. Pierce and S. Tragoudas, Enhanced Secure Architecture for JTAG Systems, IEEE Transactions on VLSI Systems (TVLSI), vol. 21, no. 7, pp. 1342-1345, July 2013.
  12. A.K. Palaniswamy  and S.Tragoudas,  An Efficient Heuristic to Identify Threshold Logic Functions, ACM Journal on Emerging Technologies in Computing (JETC), pp. 19:1- 19:17, vol. 8, issue 3, August 2012.
  13. M.N. Skoufis, S. Tragoudas,  An on-line Failure Detection Method for Data Buses using Multi-threshold Receiving Logic, IEEE Transactions on Computers, vol. 61, no. 2, pp. 187-198, Feb. 2012
  14. K. Stewart, Th. Haniotakis, and S. Tragoudas, Securing sensor networks: A novel approach that combines encoding, uncorrelation, and node disjoint transmission, Ad Hoc Networks, vol. 10, issue 3, May 2012, pp. 328-328, Elsevier.
  15. R. Adapa, S. Tragoudas, and M.K. Michael, Improved diagnosis using enhanced fault dominance, Integration, the VLSI journal, vol. 44, issue 3, pp. 217-228, June 2011.
  16. M.N. Skoufis, K. Karmakar, S. Tragoudas,  and T. Haniotakis, A data capturing method for buses on chip, IEEE Transactions on Circuits and Systems I, vol. 57, no. 7,  pp.1631-1641, July 2010.
  17. D. Jayaraman, R. Sethuram, and S. Tragoudas, Scan Shift Power Reduction by Gating Internal Nodes. J. Low Power Electronics 6(2): 311-319 (2010).
  18. E. Flanigan, S. Tragoudas, Path Delay Measurement Techniques using Linear Dependency Relationships, IEEE Transactions on VLSI Systems, vol. 18, issue 6, pp.1011-1015, June 2010.
  19. R. Adapa, S. Tragoudas, Techniques to Prioritize Paths for Diagnosis, IEEE Transactions on VLSI Systems, vol. 18, issue 4, pp. 658-661, April 2010.
  20. K. Christou, M. K. Michael, and S. Tragoudas, On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation, Journal of Electronic Testing: Theory and Applications, 2008.
  21. A. Abdulrahman and S. Tragoudas, Low-Power Multi-Core ATPG to Target Concurrency, Integration, the VLSI Design Journal, vol. 41, issue 4, pp. 459-473, July 2008.
  22. C. Song, S. Tragoudas, Identification of Critical Executable Paths at the Architectural Level, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD),  vol. 27, no. 12, pp. 2291-2302, December 2008.
  23. M.M.V. Kumar and S. Tragoudas, High Quality Transition Fault ATPG for Small Delay Defects, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD). vol. 26, no. 5, pp. 983-989, May 2007.
  24. K.J. Stewart and S. Tragoudas, Managing the power resources of sensor networks with performance considerations, Computer Communications (COMCOM), Elsevier, vol. 30, issue 5, pp. 1122-1135, March 2007.
  25. S. Padmanaban, S. Tragoudas, Implicit Grading for Multiple Path Delay Faults, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 11, issue 2, pp. 346-361, April 2006.
  26. M.D. Galanis, G. Theodoridis, S. Tragoudas and C. Goutis, A High Performance Data-Path for Synthesizing DSP Kernels, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 6, pp. 1154-1163, June 2006.
  27. Kagaris, S. Tragoudas and S. Kuriakose, A Test Architecture for Core-Based SOCs, IEEE Transactions on Computers, vol. 55, no. 2, pp. 137-149, February 2006.
  28. S.N. Neophytou, M. Michael and S. Tragoudas, Functions for Quality Transition Fault Tests and their Applications in Test Set Enhancement, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 12, pp. 3026-3035, Dec. 2006.
  29. M.M.V. Kumar, S. Tragoudas, S. Chakravarty, R. Jayabharathi, Exact Delay Fault Coverage in Sequential Logic under any Delay Fault Model, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 12, pp. 2954-2964, Dec. 2006.
  30. M.M.V. Kumar, Spyros Tragoudas, Low Power Test Generation for Path Delay Faults, Journal of Low Power Electronics, vol. 1, no. 2, pp.194-205, August 2005.
  31. S. Padmanaban and S. Tragoudas, Efficient Identification of (Critical) Testable Path Delay Faults Using Decision Diagrams, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 1, pp. 77-87, January 2005.
  32. S. Tragoudas and V. Nagarandal, Embedding Mechanisms for Large Sets of Vectors for Delay Test IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 3, pp. 488-497, March 2005.
  33. M.M. Khan and S. Tragoudas, Rewiring for Watermarking Digital Circuit Netlists, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 7, pp. 1132-1136, July 2005.
  34. M.D. Galanis, G. Theodoridis, S. Tragoudas, and C. Goutis, A Reconfigurable Coarse-Grain Data-Path for Accelerating Computationally Intensive Kernels, Journal of Circuits, Systems and Computers (JCSC), World Scientific Publishers, vol. 14,  pp. 877-893, January 2005.
  35. M.K. Michael and S. Tragoudas, Function-Based Compact Test Pattern Generation for Path Delay Faults, IEEE Transactions on VLSI Systems, vol. 13, no. 8, pp. 996-1001, August 2005.
  36. M.K. Michael, T. Haniotakis, and S. Tragoudas, A Unified Framework for Generating All Propagation Functions for Logic Errors and Events, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), pp. 980-987, vol. 23, no. 6, June 2004.
  37. J. Deodhar and S. Tragoudas, Implicit Deductive Fault Simulation for Complex Delay Fault Models IEEE Transactions on VLSI Systems, vol. 12, no. 6, pp. 636-641, June 2004.

Recent Peer-Reviewed Publications in Conference Proceedings

  1. A. Watkins and S. Tragoudas, A Highly Robust Double Node Upset Tolerant Latch,  Proceedings of the 29th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS 2016), September 19-20, 2016, Stores, CT.
  2. S. Leitner, H. Wang, and S. Tragoudas, Compressive Image Sensor Technique with Sparse Measurement Matrix, 29th IEEE International System-on-Chip Conference (SOCC), September 6-9, 2016, Seattle, WA.
  3. W. Al Jubouri, S. Tragoudas, Th. Haniotakis, Identification of delay defects on embedded paths using one current sensor, Proceedings of the 11th IEEE International Conference on Design and Technology of Integrated Systems in nanoscale era (DTIS 2016), April 12-14, 2016, Instabul, Turkey.
  4. Ph. Alladi and S. Tragoudas, Efficient Selection of critical paths for delay defects in the presence of process variations, Proceedings of the 11th IEEE International Conference on Design and Technology of Integrated Systems in nanoscale era (DTIS 2016), April 12-14, 2016, Instabul, Turkey.
  5. A. Watkins and S. Tragoudas, An Enhanced Analytical Electrical Masking Model for Multiple Event Transients, Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI 2016), pp. 99-104, May 2016, Boston, MA, to appear.
  6. P.R. Savanur, Ph. Alladi, and S. Tragoudas, A BIST Approach for Counterfeit Circuit Detection based on NBTI Degradation, Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS 2015), pp. 123-126, Oct. 12-14, 2015.
  7. S. N. Mozaffari, S. Tragoudas, and Th. Haniotakis, Fast March Tests for Defects in Resistive Memory, Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’15), July 8-10, 2015, Boston, MA, USA.
  8. J. Lenox and S. Tragoudas, Towards Trojan Circuit Detection with Maximum State Transition Exploration, Proceedings of the IEEE International On-Line Test Symposium, July 6-8, 2015, Elia, Halkidiki, Greece.
  9. L. Piece and S. Tragoudas, Unreachable Code Identification for Improved Line Coverage, Proceedings of the 2013 IEEE International Symposium on Quality of Electronic Design (ISQED 2015), March 2-4, 2015, Santa Clara, CA.
  10. P. Alladi, S. Tragoudas,  Aging-aware Critical Paths in Deep Submicron, Proceedings of the IEEE International On-Line Test Symposium, Platja d'Aro, Catalunya, Spain, July 7-9, 2014.
  11. A. Palaniswamy, S. Tragoudas, T. Haniotakis, ATPG for Transition Faults of Pipelined Threshold Logic Circuits, Proceedings of the 9th IEEE International Conference on Design and Technology of Integrated Systems in nanoscale era (DTIS 2014), 6-8 May 2014, Santorini, Greece
  12. J. Lenox and S. Tragoudas, A novel parallel adaptation of an implicit path delay grading method, Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI 2014), May 2014, Houston Texas.
  13. A. Watkins, V.N. Mudhireddy, H. Wang and S. Tragoudas, Adaptive Compressive Sensing for Low Power Wireless Sensors, Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI 2014), pp. 99-104, May 2014, Houston Texas.
  14. K. Karmakar and S. Tragoudas, Error Detection Encoding for Multi-threshold Capture Mechanism. Proceedings of the IEEE International On-Line Test Symposium, July 7-9, 2013 Chania, Greece
  15. D. Jayaraman and Spyros Tragoudas, Performance Validation Through Implicit Removal of Infeasible Paths of the Behavioral Description, Proceedings of the 2013 IEEE International Symposium on Quality of Electronic Design (ISQED 2013), March 5 - 6, 2013, Santa Clara, CA
  16. A. Mysore Somashekar and Spyros Tragoudas, Diagnosis of Small Delay Defects Arising Due to Manufacturing Imperfections Using Path Delay Measurements, Proceedings of the 2013 IEEE International Symposium on Quality of Electronic Design (ISQED 2013), March 5-6, 2013, Santa Clara, CA
  17. D. Jayaraman and Spyros Tragoudas, A Method to Determine the Sensitization Probability of a Non-Robustly Testable Path, Proceedings of the 2013 IEEE International Symposium on Quality of Electronic Design (ISQED 2013), March5-6, Santa Clara, CA
  18. C. B. Dara, T. Haniotakis, S. Tragoudas, "Low power and high speed current-mode memristor-based threshold logic gates," IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp.89-94, Oct. 2013.
  19. C. B. Dara, T. Haniotakis, S. Tragoudas, “Delay Analysis for an N-Input Current Mode Threshold Logic Gate,” International Symposium on VLSI (ISVLSI), pp. 344-349, 2012
  20. A. Watkins and S. Tragoudas, Transient Pulse Propagation Using the Weibull Distribution Function, Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), 1-3 October 2012, Austin, TX.
  21. A.M. Somashekhar, S. Gangadhar, S. Tragoudas and R. Jayabharathi, Non-enumerative generation of statistical path delays for ATPG, Proceedings of the International Conference of Computer Design (ICCD 2012), Sept. 30-Oct.3 2012.
  22. A.K. Palaniswamy and S.Tragoudas,  A scalable threshold logic synthesis method using ZBDDs, Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI’12),pp. 307-310, May 3-4, 2012,  Salt Lake City, UT.
  23. S. Gangadhar and S. Tragoudas, Accurate calculation of SET probability for hardening, Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), 1-3 October 2012, Austin, TX.
  24. A. Watkins and S. Tragoudas, Transient Pulse Propagation Using the Weibull Distribution Function, Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), 1-3 October 2012, Austin, TX.
  25. A.M. Somashekhar, S. Gangadhar, S. Tragoudas and R. Jayabharathi, Non-enumerative generation of statistical path delays for ATPG, Proceedings of the International Conference of Computer Design (ICCD 2012), Sept. 30-Oct.3 2012.
  26. A.K. Palaniswamy and S.Tragoudas,  A scalable threshold logic synthesis method using ZBDDs, Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI’12),pp. 307-310, May 3-4, 2012,  Salt Lake City, UT.
  27. P. Alladi, P.P. Mohanty and S. Tragoudas, A scalable method for arbitrary string searches in DNA sequence, Proceedings of the ISCA 4th International Conference on Bioinformatics and Computational Biology (BICoB-2012), March 12-14, 2012, Las Vegas, Nevada, USA.  
  28. L. Pierce and S. Tragoudas,  Multi-level secure JTAG architecture, Proceedings of the 17th  IEEE International On-Line Testing Symposium (IOLTS 2011), pp. 208-209, 13-15 July 2011.
  29. S. Gangadhar, S. Tragoudas, An analytical method for estimating SET propagation, Proceedings of the 29th VLSI Test Symposium, pp. 197-202, 2011
  30. S. Gangadhar, and S. Tragoudas, A probabilistic Approach to Diagnose SETs, Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS 2011), pp. 261-267, 3-5 October 2011.
  31. Kedar Karmarkar and S. Tragoudas, Error correction encoding for multi-threshold capture mechanism, Proceedings of the 17th IEEE International On-Line Test Symposium, (IOLTS 2011), pp. 157-162, 13-15 July 2011.
  32. C.B. Dara, S. Tragoudas, and T. Haniotakis. A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate, In Proc. IEEE International Symposium on Defect and Fault tolerance in VLSI and Nanotechnology (DFTS 2011), pp. 131-138, Oct. 2011.
  33. P.P. Mohanty, and S. Tragoudas. A scalable method for identifying DNA substrings using functions, Proceedings of the 3rd International Conference on Bioinformatics and Computational Biology (BICOB 2011), pp. 178-183, March 2011.
  34. D. Jayaraman, and S. Tragoudas. Occurrence probability analysis of a path at the architectural level,  Proceedings of the IEEE International Symposium on the Quality of Electronic Design (ISQED 2011), pp. 464-468, March 2011.
  35. K. Karmakar, S. Tragoudas, Scalable codeword generation for coupled buses, Proceedings of the IEEE 2010 Design Automation and Test in Europe (DATE) Conference, pp. 729-735, 8-12, March 2010, Dresden, Germany.
  36. S. Gangadhar, S. Tragoudas, A Novel Probabilistic SET Propagation Method, in Proceedings of the 10th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 258-263, March 2010.
  37. D. Jayaraman, R. Sethuram, and S. Tragoudas, Gating internal nodes to reduce power during scan shift, Proc. of the 2010 ACM Great Lakes Symposium on VLSI, pp. 79-84, October 2010.
  38. S. Gangadhar, S. Tragoudas, Probabilistic methods for the impact of an SET in combinational logic, Proceedings of the 16th  IEEE International Online Testing Symposium (IOLTS), pp.41-46, July 2010.
  39. M.N.  Skoufis, S. Tragoudas,  On-line Detection of Random Voltage Perturbations in Buses with Multiple-threshold Receivers, Proceedings of the 16th  IEEE International Online Testing Symposium (IOLTS), pp.249-254, July 2010.
  40. A.K. Palaniswamy, M.K. Goparaju, S. Tragoudas, Scalable identification of threshold logic functions, Proc. of the 2010 ACM Great Lakes Symposium on VLSI, pp. 269-274, October 2010.
  41. E. Flanigan, S. Tragoudas, and A. Abdulrahman, Scalable Compact Test Pattern Generation for Path Delay Faults based on Functions, Proc. of the 27th IEEE VLSI Test Symposium (VTS 2009), pp. 140-145, 3-7 May 2009.