Programming Non-Coherent Cache Architectures | Center for Embedded Systems | SIU

Non-Coherent Cache multi-core architecture is expected to be more popular since cache coherency protocols do not scale well with the increasing number of cores. On NCC architecture, multi-threaded programs cannot be executed directly since the programming paradigm assumes the coherent caches. Since multi-threaded programming paradigm has been widely used and known be easier to program, this project aims to enable efficient execution of multi-threaded programs on NCC architecture. To execute such programs on NCC architecture, each load and store instruction in a program should be converted to coherent load and coherent store function, where the overhead of maintaining cache coherency by software takes place. Our compiler analysis can find load and store instructions that only access local data. By being able to figure out when the cache coherence management is not needed, we can optimize the overhead of coherent load and store functions. Further, programming practices, like the use of semaphores will make it easier for us to discern and optimize the communication between threads.