Early Clock On-chip Mechanisms and Architectures for Buses | Center for Embedded Systems | SIU

Early latching mechanism relies on modeling of the transient response of coupled bus lines. External sources of noise may cause unpredictable deviation in the line voltages resulting in bit errors. The proposed technique is capable of detecting certain errors. The error correction can be achieved by adding redundant bits. The codeword selection process is formulated as a graph based problem. The technique is not scalable for wide buses due to exponential size of the graph. Scalability of the codeword selection algorithms can be improved by roughly estimating conflict count, using binary decision diagrams to perform certain set operations and using iterative node addition instead of node deletion.