Design and Thermal Modeling of Energy-Efficient Multi-core Architecture

Main Content

PIs: Sarma Vrudhula, Aviral Shrivastava
Type: New

Power-efficiency and scalability are the two key design metrics in processor architectures. We propose to realize high degree and yet scalable concurrency through a Hierarchy of Multi-core and within-core Programmable Accelerators (HMPA). At the top-level; the HMPA architecture consists of several cores, much like Chip Multi Processors, or CMPs of today. Each core in turn, has a tightly coupled programmable accelerator attached to it. From the power-efficiency perspective, a non-programmable or ASIC accelerator may be the best; but lack of programmability severely limits their applicability. One of the most promising – programmable, yet power-efficient – accelerator technologies is Coarse Grain Reconfigurable Architecture or CGRA. CGRA is essentially an array of Processing Elements (PEs), like ALU and multiplier, interconnected as a 2D grid, together with fast and low-power scratch pad memories for instruction and data. Like all modern architectures, this is also likely to suffer from thermal problems. Therefore we will develop thermal model for the HMPA architecture. This will be needed even in the early phases of the design to determine the number of cores that can be sustained for a given power-efficiency of the packaging.