Development of High-Speed and High-Resolution ADC | Center for Embedded Systems | SIU

The long-term goal of the proposed research is to investigate techniques for implementing ADC circuits with effective resolution bandwidth (ERBW) of 2GHz and effective number of bits (ENOB) of 12 or higher. The design approach to be investigated in the project is to combine sub-sampling, time-interleaved structure and pipeline ADCs with digital correction techniques. The work for the current proposed year focus on the design of sample-and-hold (S&H) circuits and how to minimize clock jitters, which include jitter due to cross-talk and noise at power supply and ground, and random jitter of the clock driver circuit.