Application Mapping For CGRA

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PIs: Aviral Shrivastava, Sarma Vrudhula
Type: New

Power-efficiency is becoming the most important concern in computation. CGRAs or Coarse Grain Reconfigurable Architectures are simply a 2-D array of processing elements or PEs. Each PE is simply an ALU plus a small register file. Each PE can operate on the output of the neighboring PEs from the last cycle. Since little more than a PE power is needed to perform an arithmetic operation, CGRAs are extremely power-efficient, with power-efficiencies reaching more than 100 Giga operations per second per watt of power. The reason why CGRAs are so power-efficient is because the hardware is very simple. This is because there is no control unit in hardware to manage memory, or detect and correct hazards, or dynamically assign instructions to PEs; everything must be determined statically by the compiler. In addition to the regular tasks of a compiler, a CGRA compiler should also perform explicit pipelining, scheduling, placement, routing, and memory management. As a result compilation for CGRAs is difficult and existing compilers are unable to produce high quality mappings. The objective of this proposal is to develop compilation techniques to map loops of the main application onto the CGRA, and achieve extremely high-performance and power-efficient execution.